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April 1997 PRELIMINARY
ML4901 High Current Synchronous Buck Controller
GENERAL DESCRIPTION
The ML4901 high current synchronous buck controller has been designed to provide high efficiency DC/DC conversion for next generation processors such as the Pentium(R) Pro from Intel(R). The ML4901 controller, when combined with 2 external MOSFETs, generates output voltages between 2.1V and 3.5V from a 12V supply. The output voltage is selected via an internal 4-bit DAC. Output currents in excess of 14A can be attained at efficiencies greater than 90%. The ML4901 can be enabled/disabled via the SHDN pin. While disabled, the output of the regulator is completely isolated from the circuit's input supply. The ML4901 employs fixed-frequency PWM control combined with a dual mode control loop to provide excellent load transient response.
FEATURES
s
Designed to meet Pentium(R) Pro power supply requirements DC regulation to +1% maximum Proprietary circuitry provides transient response of +5% maximum over 300mA to 14A load range Programmable output voltage (2.1V to 3.5V) is set by an onboard 4-bit DAC Synchronous buck topology for maximum power conversion efficiency Fixed frequency operation for easier system integration Integrated antishoot-through logic, short circuit protection, and UV lockout Shutdown control provides load isolation
s s
s
s
s s
s
BLOCK DIAGRAM (Pin Configuration Shown for 16-Pin SOIC Version)
15
VDD
+
10.4V PROTECT
16
-
UVLO
+ -
P DRV
14
4.4V
CONTROL LOGIC
N DRV
13
35A
+ -
PWR GND
12
SHDN
5
COMP 200kHz
+ -
11
D0
1
VFB VDAC -95mV ISENSE
9
D1
2
D2
3
+ -
10
D3
4
PWR GOOD
6
4 BIT DAC
VDAC
+ -
VDAC + 10% VDAC + 3% VFB VDAC - 10% VDAC - 3%
8
+ -
VDAC + 3% VFB VDAC - 3%
+ -
+ -
3.5V REFERENCE GND
VREF
7
1
ML4901
PIN CONFIGURATION
ML4901 16-Pin Narrow SOIC (S16N)
D0 D1 D2 D3 SHDN PWR GOOD VREF GND 1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 PROTECT VDD P DRV N DRV PWR GND COMP ISENSE VFB D0 D1 D2 D3 NC SHDN NC PWR GOOD VREF GND
ML4901 20-Pin TSSOP (T20)
1 2 3 4 5 6 7 8 9 10 TOP VIEW 20 19 18 17 16 15 14 13 12 11 PROTECT VDD NC P DRV N DRV PWR GND NC COMP ISENSE VFB
PIN DESCRIPTION (Pin Number in Parentheses is for TSSOP Version)
PIN# NAME FUNCTION PIN# NAME FUNCTION
1 (1) 2 (2) 3 (3) 4 (4) 5 (6) 6 (8)
D0 D1 D2 D3 SHDN PWR GOOD
LSB input to the DAC which sets the output voltage Input to the DAC which sets the output voltage Input to the DAC which sets the output voltage MSB input to the DAC which sets the output voltage Grounding this pin shuts down the regulator This open drain output goes low whenever SHDN goes low or when the output is not within +10% of its nominal value Bypass connection for the internal 3.5V reference
8 (10) 9 (11)
GND VFB
Analog signal ground Output voltage feedback pin Current sense input Connection for the compensation network Power ground Synchronous rectifier driver output Buck switch driver output 12V power supply input Connection for the integrating current limit network and the UVLO monitor for the 5V supply
10 (12) ISENSE 11 (13) COMP 12 (15) PWR GND 13 (16) N DRV 14 (17) P DRV 15 (19) VDD 16 (20) PROTECT
7 (9)
VREF
2
ML4901
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VDD .......................................................................................... 13.5V Peak Driver Output Current ....................................... 2A VFB Voltage ....................................... GND - 0.3V to 5.5V ISENSE Voltage ................................... GND - 0.5V to 5.5V All Other Analog Inputs .......... GND - 0.3V to VDD + 0.3V SHDN Input Current .............................................. 100A Junction Temperature .............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering, 10 sec) ...................... 260C Thermal Resistance (JA) 16-Pin Narrow SOIC ...................................... 100C/W 20-Pin TSSOP ................................................. 143C/W
OPERATING CONDITIONS
Temperature Range ........................................ 0C to 70C VDD Range ............................................... 11.4V to 12.6V PROTECT (5V Supply) Range .................... 4.75V to 5.25V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VDD = 12V, PROTECT = SHDN = 5V, TA = Operating Temperature Range (Note 1)
SYMBOL REFERENCE VREF Output Voltage Line Regulation UV LOCKOUT VDD Start-up Threshold VDD Hysteresis PROTECT (5V) Start-up Threshold PROTECT (5V) Hysteresis SHUTDOWN Input Low Voltage Input High Voltage Delay to Output POWER GOOD COMPARATOR Output Voltage in Regulation Output Voltage out of Regulation Output Voltage in Shutdown BUCK REGULATOR Oscillator Frequency Duty Cycle Ratio DAC (D3-D0) Code = 0100, VFB = 0V DAC (D3-D0) Code = 0100, VFB > 3.193V DAC (D3-D0) Input Low Voltage DAC (D3-D0) Input High Voltage 2.0 160 80 200 230 90 0 0.8 kHz % % V V 5k pull-up to 5V VFB < 90% VDAC or >110% VDAC SHDN = 0V, 5k pull-up to 5V 4.8 0.4 0.4 V V V 2.0 50 0.8 V V ns 10.0 300 4.25 400 10.4 450 4.4 450 10.8 600 4.55 500 V mV V mV 11V < VDD < 13V 3.51 3.535 0.5 3.56 V mV/V PARAMETER CONDITIONS MIN TYP MAX UNITS
3
ML4901
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER BUCK REGULATOR (continued) VFB Threshold Voltage DAC (D3-D0) Code = 0000 DAC (D3-D0) Code = 0001 DAC (D3-D0) Code = 0010 DAC (D3-D0) Code = 0011 DAC (D3-D0) Code = 0100 DAC (D3-D0) Code = 0101 DAC (D3-D0) Code = 0110 DAC (D3-D0) Code = 0111 DAC (D3-D0) Code = 1000 DAC (D3-D0) Code = 1001 DAC (D3-D0) Code = 1010 DAC (D3-D0) Code = 1011 DAC (D3-D0) Code = 1100 DAC (D3-D0) Code = 1101 DAC (D3-D0) Code = 1110 DAC (D3-D0) Code = 1111 ISENSE Threshold Voltage ISENSE Hysteresis PROTECT Discharge Current PROTECT Leakage Current Transition Time, N DRV and P DRV SUPPLY VDD Current SHDN = 0V DAC (D3-D0) Code = 0000 SHDN = 5V, VFB = 5V SHDN = 5V, VFB = 0V, CL = 5000pF
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
(Continued)
CONDITIONS MIN TYP MAX UNITS
3.500 3.400 3.300 3.200 3.100 3.000 2.900 2.800 2.700 2.600 2.500 2.400 2.299 2.198 2.097
3.535 3.434 3.333 3.232 3.131 3.03 2.929 2.828 2.727 2.626 2.525 2.424 2.323 2.222 2.121
3.570 3.468 3.366 3.264 3.162 3.060 2.958 2.856 2.754 2.652 2.550 2.448 2.347 2.246 2.145 0.8
V V V V V V V V V V V V V V V V mV mV A nA ns
-85
-95 3
-105
V(ISENSE) = -120mV
35 +100
CL = 5000pF, 10-90%
40
300 1 30
450 2
A mA mA
4
ML4901
FUNCTIONAL DESCRIPTION
The ML4901 PWM controller permits the construction of a simple yet sophisticated power supply for Intel's Pentium(R) Pro microprocessor which meets the guidelines of Intel's Application Note AP-523. This can be built either as a Voltage Regulator Module (VRM) or as dedicated motherboard circuitry. The ML4901 controls a P-channel and an N-channel MOSFET in a synchronous buck regulator circuit, to convert a 12V input to the voltage required by the microprocessor. The output voltage can be any set to any one of 15 output voltages from 2.1V to 3.5V, in steps of 100mV, as selected by an onboard DAC. Other features which facilitate the design of DC-DC converters for any type of processor include a trimmed 1% reference, special transient-response optimization in the feedback paths, a shutdown input, input and output power good monitors, and overcurrent protection. 4-BIT DAC The inputs of the internal 4-bit DAC come from open collector signals provided by the Pentium Pro. These signals specify what supply voltage the microprocessor requires. The output voltage of the buck converter is compared directly with the DAC voltage to maintain regulation. D3 is the MSB input and D0 is the LSB input of the DAC. The output voltage set by the DAC is 1% above the Pentium Pro's nominal operating voltage to counteract the effects of connector and PC trace resistance, and of the instantaneous output voltage droop which occurs when a transient load is applied. The output of the DAC therefore ranges from 2.121V to 3.535V in 100mV steps. For code 1111, the P DRV output is disabled, and the output voltage is zero. VOLTAGE FEEDBACK LOOP The ML4901 contains two control loops to improve the load transient response. The output voltage is directly monitored via the VFB pin and compared to the desired output voltage set by the internal 4-bit DAC. When the output voltage is within +3% of the DAC voltage, the proportional control loop (closed by the voltage error amplifier) keeps the output voltage at the correct value. If the output falls below the DAC voltage by more than 3%, one side of the transient loop is activated, forcing the output of the ML4901 to maximum duty cycle until the output comes back within the +3% limit. If the output voltage rises above the DAC voltage by more than 3%, the other side of the transient loop is activated, and the upper MOSFET drive is disabled until the output comes back within the +3% limit. During start-up, the transient loop is disabled until the output voltage is within -3% of the DAC voltage. POWER GOOD (PWR GOOD) An open drain signal is provided by the ML4901 which tells the microprocessor when the entire power system is functioning within the expected limits. PWR GOOD will be false (low) if either the 5V or 12V supply is not in regulation, when the SHDN pin is pulled low, or when the output is not within +10% of the nominal output voltage selected by the internal DAC. When PWR GOOD is false, the PWR GOOD voltage window is held to +3%; when PWR GOOD is true (high), the window is expanded to +10%. Using different windows for coming into and going out of regulation makes sure that PWR GOOD does not oscillate during the start-up of the microprocessor. INTERNAL REFERENCE The ML4901 contains a 3.535V, temperature compensated, precision band-gap reference. The VREF pin is connected to the output of this reference, and should be bypassed with a 100nF to 220nF ceramic capacitor for proper operation. OVERCURRENT PROTECTION When the output of the buck converter sees an overcurrent condition (IOUT exceeds the current limit set point ISET), the ML4901 will operate in a "hiccup" mode until the overcurrent condition has been removed. During an overcurrent condition, a current sink within the ML4901 draws a small current (35A) out of the PROTECT pin for the time during which IOUT > ISET. If this current sink is activated over a number of cycles, the voltage on the PROTECT pin will drop below 4V, signalling a sustained overcurrent or short circuit at the load. This will cause the P DRV output to turn off. The converter will remain in an off state until the capacitor attached to the PROTECT pin has charged back to 4.4V, at which time the converter is re-enabled and tries to resume normal operation. If the fault causing the overcurrent condition has not been cleared, the overcurrent protection cycle will repeat. UNDERVOLTAGE LOCKOUT The ML4901 has undervoltage lockout protection circuits for both the 12V (VDD) and 5V (PROTECT) supplies. The hysteresis voltage is typically 450mV for each supply. During an input undervoltage condition, the internal reference and voltage monitor circuits remain in operation, but P DRV and N DRV are disabled and the PWR GOOD output will be false (low). COMPENSATION This pin connects to the output of the transconductance amplifier which forms the gain block for the ML4901's proportional control loop. An RC network from this pin to GND is used to compensate the amplifier.
5
ML4901
DESIGN CONSIDERATIONS
This section is a quick-check guide for getting ML4901 circuits up and running, with a special emphasis on Pentium Pro applications. All component designators refer to the circuit shown in Figure 1. COMPENSATION The R and C values connected to the COMP pin for loop compensation are 330k and 33pF, respectively. These values yield stable operation and rapid transient response for a most values of L and COUT (1H to 5H, 1200F to 10,000F), and will generally not need to be altered. If changes do need to be made, note that the drive capability of the transconductance error amplifier is typically 10A, its ZOUT is 10 M, and its unity-gain frequency is approximately 10 MHz. INPUT AND OUTPUT CAPACITORS The input and output capacitors used in conjunction with the ML4901, especially in Pentium Pro VRM applications, must be able to meet several criteria: 1. The input capacitors must be able to handle a relatively high ripple current 2. The output capacitors must have a low Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) 3. The output capacitors must be able to hold up the output during the time that the current through the buck inductor is slewing to meet a transient load step. The circuit's input bypass capacitance should be able to handle a ripple current equal to 0.5 x ILOAD. If the converter sees load peaks only occasionally, and for less than 30 seconds at a time during those intervals, then aluminum electrolytic or OS-CON(R) input capacitors need only be sized to accommodate the average output load. Note that tantalum input capacitors have much less thermal mass than aluminum electrolytics, so this relaxation of ripple current requirements may not apply to them. During a 30A/s load transient, it is not practical for a buck converter to slew its output current fast enough to regulate the instantaneous output voltage required by this application. During the first few microseconds following such a load step, the output capacitance of the converter must act as passive energy storage. In delivering its energy to the load, the output capacitance must not introduce any considerable impedance, or its purpose will be defeated. A total voltage aberration during load transients of 5% is allowed (see Intel AP-523). The voltage transient due to ESL and ESR is:
V = ESR x IOUT + ESL x
ESL (66mV). To meet this requirement, the output ESR should not exceed:
ESR(MAX) = 100mV = 7.3mW 137 A .
(2)
With the effects of ESL limited to 2% of 3.3V, the maximum ESL is:
ESL(MAX) = 1ms 66mV = 22nH . 30 A
(3)
Achieving these low a values of ESL and ESR is not trivial; doing so typically requires using several high-quality capacitors in parallel. Dedicated power and ground planes are helpful as well. The output capacitance should have a value of > 2200F to hold the output voltage relatively constant (<50mV of sag) until the current in the buck inductor can catch up with the change in output current. To meet the ESR and ESL requirements, the actual output capacitance will usually be significantly greater than this theoretical minimum. These capacitors can be of all one type, or a combination of aluminum electrolytic, OS-CON, and tantalum devices. OVERCURRENT PROTECTION Current sense resistor R1 is used to monitor the inductor current during the off period, i.e., while current is flowing through the synchronous rectifier (or Schottky diode, if no synchronous rectifier MOSFET is used). The internal current sense comparator has been designed to provide in excess of 14A of output current when used with a 6m resistor. R1 must be a low inductance part such as Dale/ Vishay's type WSL-2512-.0061%. This is a 6m surface mount part rated at 1 Watt. Using a PCB trace as a current sense element is not recommended due to the high temperature coefficient of copper, and due to etching and plating tolerances which can occur from board to board. The R and C values connected to the PROTECT pin for setting the current limit delay and the off-time of the hiccup mode are 100k and 1F, respectively. These values will protect most MOSFETs from overheating during a short circuit condition. If it is necessary to change the ratio of ON and OFF times during overcurrent conditions, this can be done by selecting a different value for C13. Larger values of C13 will increase the delay between retry attempts (the length of the "hiccup"). The voltage across current sense resistor R1 must be Kelvin-sensed. This ensures that the ML4901 monitors only the voltage across this resistor and not the voltage drops or inductive transients in the PCB traces which carry current into and out of this resistor. The two pins of the ML4901 which must be Kelvin-connected to the sense resistor are ISENSE and GND. There is no connection inside the ML4901 between GND and PWR GND. This is to facilitate the requisite Kelvin-sensing of the voltage across R1.
LMb N
g FGH
di dt
IJ OP KQ
(1)
For example, assume that a 3.3V output has 3% of the output's V contributed by ESR (100mV)and 2% by the
6
ML4901
12VIN
C11 22F 25V C10 220nF 16V
5VIN OUTEN UP#
D1 BAW56 R4 1k C13 1F 16V C12 220nF 16V 3X C1 1800F 10V C2 C3
ML4901
1 2 3 4 5
R5 100k
VID0 VID1 VID2 VID3 PWRGD
C14 1nF C8 220nF 16V
D0 D1 D2 D3 SHDN PWR GOOD VREF GND
PROTECT 16 VDD 15 P DRV 14 N DRV 13 PWR GND 12 COMP 11 ISENSE 10 VFB 9
R3 330k C9 33pF Q2 R1 6m 1W 4X C4 1800F 10V C5 C6 C7 Q1 L2 2.5.H
VCCP
6 7 8
VSS
Figure 1. Pentium Pro VRM Circuit
Because of this, there must be a good electrical connection between the ML4901 PWR GND and GND pins. At the same time, PWR GND must have a low impedance connection to the ground plane used on the board, as high instantaneous currents will flow in PWR GND when N DRV L and N DRV H switch the capacitive loads of the output MOSFET gates. A layout technique which satisfies these requirements is to return PWR GND to the grounded end of R1 using a high current Kelvin connection. Figure 2 shows one successful implementation of these PCB layout requirements. ISENSE is an input to a medium-speed, high-sensitivity comparator. It is often helpful to shield the trace running from R1 to ISENSE with a "guard trace" to circuit ground. The compensation components R3 and C9 are highimpedance nodes connected to the output of the voltage loop error amplifier. These components should be kept in close proximity to the ML4901. C9 should be returned to GND, not to PWR GND or the ground plane of the PC board. It may be helpful to shield the trace running from R3 to COMP with a "guard trace" to circuit ground. Keep the VREF bypass capacitor C8 close to the ML4901. Ensure that its ground connection is to GND, not PWR GND or the ground plane of the PCB.
The VDD bypass capacitors C10 and C11 should be returned to PWR GND or to the PC board ground plane. They should not be returned to GND due to high transient currents which could interfere with the current sensing function. If a given design uses power MOSFETs in an SO-8 package style, keep in mind that their thermal dissipation capability is largely dictated by the copper area available to their drains. A good layout will maximize this area.
TO ISENSE TO PWR GND TO GND
TO SYNCHRONOUS RECTIFIER MOSFET SOURCE
SENSE RESISTOR
POWER GROUND RETURN (GROUND PLANE)
Figure 2. Kelvin Sense Connections
7
ML4901
PHYSICAL DIMENSIONS
inches (millimeters)
Package: S16N 16-Pin Narrow SOIC
0.386 - 0.396 (9.80 - 10.06) 16
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
Package: T20 20-Pin TSSOP
0.251 - 0.262 (6.38 - 6.65) 20
0.169 - 0.177 (4.29 - 4.50) PIN 1 ID
0.246 - 0.258 (6.25 - 6.55)
1 0.026 BSC (0.65 BSC) 0.043 MAX (1.10 MAX) 0 - 8
0.033 - 0.037 (0.84 - 0.94)
0.008 - 0.012 (0.20 - 0.30)
SEATING PLANE
0.002 - 0.006 (0.05 - 0.15)
0.020 - 0.028 (0.51 - 0.71)
0.004 - 0.008 (0.10 - 0.20)
ORDERING INFORMATION
PART NUMBER ML4901CS ML4901CT
(c) Micro Linear 1997. Co., Ltd.
TEMPERATURE RANGE 0C to 70C 0C to 70C
PACKAGE 16-Pin Narrow SOIC (S16N) 20-Pin TSSOP (T20)
is a registered trademark of Micro Linear Corporation. Pentium is a registered trademark of Intel Corporation. OS-CON is a registered trademark of Sanyo Electric
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565761; 5,592,128; 5,594,376. Japan: 2,598,946; 2,619,299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4901-01
8

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